Senior Digital Design Engineer Job in Germany with Visa Sponsorship

Job Position: Senior Digital Design Engineer Job in Germany with Visa Sponsorship
Company: European Tech Recruit
Location: North Rhine-Westphalia, Germany

We’re working with an award-winning semiconductor company that’s doing something genuinely exciting—they’ve developed and patented a breakthrough wideband transceiver microchip that’s powering the next generation of ultrafast wireless tech (think 5G-Advanced and 6G infrastructure). If you’re a Digital Design Engineer who wants to work on cutting-edge technology that’s actually shaping the future of connectivity, this could be a great fit.

What You’ll Be Doing

We’re looking for engineers with solid experience in either frontend RTL design or backend physical implementation—or even better, both. You’ll be working on high-performance digital and mixed-signal ICs using advanced process nodes like 22FDX and other FinFET/FD-SOI technologies.

Day-to-day, you’ll be

• Taking ownership of RTL design and micro-architecture for digital subsystems (DSP blocks, control logic, interfaces—that kind of thing)
• Working through the backend flow: synthesis, floorplanning, P&R, timing closure, and signoff tasks like STA, LVS, and DRC
• Collaborating with physical design teams to make sure handoffs are smooth and digital/mixed-signal boundaries are clean
• Helping integrate digital blocks with analog and mixed-signal subsystems
• Writing documentation, building testbenches, and jumping in on post-silicon bring-up and debugging when needed

What We’re Looking For

You should be comfortable with:

• RTL design in SystemVerilog or VHDL, plus digital verification and scripting (Python, Tcl, etc.)
• EDA tools from Cadence, Synopsys, or Mentor—especially for synthesis, timing analysis, and backend work
• Low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design
• Hands-on physical implementation: floorplanning, P&R, clock tree synthesis, STA, DRC, LVS
• Modern process nodes—ideally 22FDX, 16/12nm FinFET, or similar
• Mixed-signal integration, top-level assembly, and testability concepts (DFT experience is a bonus)
• Strong problem-solving skills and the ability to work independently without needing your hand held

Experience Level

• Mid-Level: 3–5 years in digital IC design
• Senior-Level: 6+ years, with proven experience owning IP/SoC blocks or leading backend flows

Qualifications

MSc or PhD in Electrical Engineering, Microelectronics, or a related field

How to Apply

Interested? Hit the Click “Apply Now” and let’s get the ball rolling.

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